1. Field
This invention relates to phase interpolators, and more specifically, to improving the linearity of the phase interpolators using capacitive elements.
2. Background
A receiver needs to determine when to sample the data signal transmitted from one chip to another or from one core to another within a single chip. The receiver determines this using a clock signal sent with the data signal. However, in systems with higher signal rates or no explicit clock signal present, the receiver requires a clock alignment circuit such as a phase-locked loop (PLL). A phase interpolator-based clock data recovery circuit (CDR) is an alternative system that can generate precisely-aligned clocks by selecting pairs of reference phases and interpolating between them to recover the data from the serialized data signal.
One of the most commonly used CDR architectures is a dual-loop structure consisting of a cascade of two loops, a core PLL and a peripheral CDR loop. A PLL generates multiple phases, which are used by the phase interpolator in the CDR loop to introduce a controlled phase shift in the recovered clock. The negative feedback of the CDR loop forces the recovered clock phase to the middle of the received data.
Although the simplicity of the CDR architecture has led to its widespread usage, one of the disadvantages of this architecture includes excessive clock jitter due to nonlinearity of the phase interpolator. In one example, the nonlinearity of the phase interpolator is illustrated in a representative transfer function shown in FIG. 1. Ideally, the minimum phase step is equal to φLSB, but interpolator nonlinearity introduces a much larger phase jump, φMAX, that severely degrades the recovered clock jitter. Differential nonlinearity (DNL) is often used to measure the deviation from the ideal step width.